1. Field of the Invention
The present invention relates to a semiconductor power device, and particularly to a semiconductor device such as an Insulated Gate Bipolar Transistor (IGBT) or a power MOSFET (insulated gate field effect transistor). More particularly, the invention relates to a structure for improving a driving current quantity, a latch-up immunity and turn-off characteristics of a power device.
2. Description of the Background Art
Power devices have been used in the fields of converting and controlling electric powers. Such power devices include a MOS gate device receiving a voltage at an insulated gate for performing a switching operation. MOS gate devices include an IGBT (Insulated Gate Bipolar Transistor) and a MOSFET (insulated gate field effect transistor). A semiconductor switch of such power device is required to have characteristics of fast operation (fast switching operation) as well as large current driving and high breakdown voltage.
A reference 1 (Japanese Patent Laying-Open No. 07-058320) discloses the following structure for the purpose of reducing a turn-off time of the IGBT to increase an operation frequency. Reference 1 discloses, as a conventional structure, the following structure. A p-type base contact layer is arranged surrounding an n-type emitter layer, and is contacted with a p-type base layer. The p-type base contact layer and the n-type emitter layer are both coupled to an emitter electrode. The p-type base contact layer discharges minority carriers (holes) to the emitter electrode during turn-off. An n-type buffer layer is formed under a p-type collector layer. This buffer layer prevents the discharging of minority carriers to an n−-type drift layer when majority carriers arc discharged from the collector layer to a collector terminal during turn-off. In the case of employing the n-type buffer layer, if a buffering effect of the buffer layer is made so high, the efficiency of injection of the minority carriers into the drift layer during turn-on is lowered to lower a conductivity modulation effect, leading to an increased on-resistance and therefore an increased on-voltage. As a structure for avoiding such disadvantage, Reference 1 discloses a shorted collector structure. In this shorted collector structure, an n-type collector short layer is arranged surrounding an outer perimeter of a p-type collector. Both the p-type collector layer and the n-type collector short layer are commonly coupled to a collector electrode. In this collector short structure, majority carriers flow into the collector short layer during turn-off, but the collector short layer absorbs the minority carriers and thereby suppresses generation of the minority carriers so that the turn-off time is reduced.
The IGBT generally includes a p-type collector layer, n-type buffer layer, n−-type drift layer, p-type base layer and n-type emitter layer. This npn structure accompanies a parasitic thyristor. A latch-up phenomenon may be caused in which the parasitic thyristor is turned on by a voltage drop at a base region of the IGBTeference 2 (Japanese Patent National Publication No. 09-503626: International Patent Publication WO 95/24055) discloses a structure aimed to improve this latch-up immunity.
In Reference 2, a heavily doped p+-type region is arranged beneath an n+-type source layer in a p-type base region formed in an n−-type drift layer. The heavily doped p+-type region serves to reduce a resistance value of a p-type base region, thereby to reduce a voltage drop at a junction between the source and base regions to improve latch-up immunity.
Reference 3 (Japanese Patent Laying-Open No. 2000-286416) discloses a structure aim1ng to increase an on-current and to improve the latch-up immunity. In Reference 3, a collector layer, an emitter layer and a gate electrode are each formed into a ring shape. The emitter layer (source layer) has a gear-like form having convex and concave portions, or is formed of island-like portions each isolated from the others. A base resistance of a portion under the emitter region is reduced, and a hole current is radially discharged from a collector layer formed at a central portion to reduce the current density of the hole current, for improving a latch-up immunity.
Reference 1 has pointed out the following problem occurring when the shorted collector structure is applied to a lateral IGBT structure. During the turn-off, majority carriers pass under the p-type collector layer, and flow into the n-type collector short layer, and therefore into the p-type collector layer also. Accordingly, minority carriers an increased quantity are injected into the n−-type drift layer. For eliminating the problem of the shorted collector structure in the lateral IGBT structure, Reference 1 places an MOS transistor (insulated gate field effect transistor) having a sub-gate in the p-type collector layer, and couples the collector layer to a collector charge extraction layer via the sub-gate MOS transistor. The charge extraction layer is coupled to the collector terminal. In the sub-gate structure, the n-type source layer of the MOSFET is arranged adjacent to the p-type collector layer, and these layers are coupled by the common electrode, and thereby n-type carriers in the n-type source layer are converted into p-type carriers in the p-type collector layer. During the turn-off, the MOS transistor of the sub-gate structure is kept off to keep the p-type collector layer in this sub-gate in an electrically floating state, and the p-type collector layer is isolated from the charge extraction layer. Majority carriers (electrons) are pulled out to the collector terminal via the charge extraction layer. Meanwhile, the p-type collector layer and the underlying p-well (p-base) are in the electrically floating state, and a pn junction between the well and the drift layer is kept in a reversely biased state (not exceeding a built-in voltage), and suppresses injection of minority carriers.
However, tin the structure disclosed in Reference 1, an additional circuit is required for controlling a potential of the sub-gate separately from the gate (main gate) of the IGBT, which increases a scale of the control circuitry. In the IGBT element, the sub-gate and the main gate terminal are separately provided, which increases a layout area. In the structure disclosed in Reference 1, the majority carriers (electrons) pass under the p-type base layer, and are absorbed into the charge extraction layer. However, no consideration is given to a latch-up phenomenon by a parasitic thyristor between the p-type collector layer, underlying p-well, n−-type drift layer and n-type emitter layer.
In the structure disclosed in Reference 2, it is intended to reduce the resistance value of the p-type base region by the heavily doped p+-type region arranged beneath the n-type source layer. However, Reference 2 discusses only a vertical device structure, and no consideration is given to application to a lateral device structure. In addition, Reference 2 considers a structure for avoiding of latch-up due to a parasitic thyristor in the vertical device structure, but does not consider a structure for increasing a driving current.
In the structure disclosed in Reference 3, the emitter region is formed in a gear-like shape or is formed of separate island-like portions for avoiding the latch-up, but there is room for improvement for increasing the driving current and reducing the turn-off time.